A digital electrical circuit is designed typically to function in accordance with the operating characteristics of one of a variety of logic families. These include a CMOS transistor-based family ("CMOS digital circuits") and any one of several bipolar junction transistor-based families ("bipolar digital circuits"), such as transistor-transistor logic (TTL) and emitter-coupled logic (ECL). Each logic family has different operating characteristics that render the family suitable for use under different operational constraints Although such circuits may be manufactured from any of a variety of semiconductor materials that include silicon and gallium arsenide, the following descriptions refer by way of example to the operating characteristics of circuits manufactured from silicon.
It is sometimes desirable to employ bipolar and CMOS digital components in different parts of a single digital integrated circuit, which is typically called a bipolar-CMOS (Bi-CMOS) circuit. As a first example, CMOS digital integrated circuits can be manufactured at such large scale integration that the operating frequencies of such circuits are limited more by the capacitance between interconnected CMOS transistors than by the switching speeds of the transistors themselves. Bipolar transistors configured as current amplifiers can be used to compensate for the rate-limiting capacitances in such large-scale CMOS digital circuits and thereby form Bi-CMOS digital circuits having higher operating frequencies than the CMOS digital circuits. As a second example, large-scale integration of CMOS and bipolar transistors in a single integrated circuit provides the capability of manufacturing "complete" electronic systems on such integrated circuits. The operating characteristics of uncompensated bipolar and CMOS digital circuits differ, however, in several respects and thereby render them difficult to interface.
In the case of bipolar digital circuits designed in accordance with the ECL family, a first difference is in the logic signal levels of ECL and bipolar digital circuits. If, for purposes of comparison, such circuits are operated from a +5 volt supply, the high and low logic signal levels of ECL circuits would typically be +4.1 and +3.3 volts, respectively; whereas, the high and low logic signal levels of high-density CMOS circuits would typically be +5 volts and 0 volts, respectively. A second difference is that the logic signal voltage levels of ECL circuits change in response to temperature variations; whereas, the logic signal voltage levels of CMOS circuits are substantially constant over a wide range of operating temperatures. A third difference is that the n- and p-channel field-effect transistors employed in CMOS circuits typically have different threshold voltage characteristics and are very sensitive to variations in manufacturing processes; whereas, the bias voltage of the npn bipolar junction transistors employed in ECL circuits are comparatively insensitive to variations in manufacturing processes. The different threshold voltage characteristics of the n- and p-channel transistors in a CMOS digital circuit can cause the low and high logic signalthreshold levels to vary between 30% and 70% of the supply voltage and thereby cause different propagation delays for the high and low logic signals.
An interface circuit that provides functional compatibility between an ECL circuit driving a CMOS circuit should, therefore, compensate for the different ECL and CMOS logic signal voltage levels, compensate for temperature-related changes in ECL logic signal voltage levels, and provide a common CMOS logic signal threshold. U.S. Pat. No. 4,578,600 of Magee describes a CMOS buffer circuit that provides a common logic threshold for the high and low CMOS logic signal levels. The logic threshold is purportedly substantially independent of the different threshold voltage characteristics of n- and p-channel field-effect transistors used in the circuit.
The CMOS buffer circuit of Magee comprises a prior art CMOS inverter 10, a diagram of which is shown in FIG. 1. Inverter 10 includes a n-channel transistor 12 and a p-channel transistor 14 whose respective gate terminals 16 and 18 are electrically connected and whose respective drain terminals 20 and 22 are electrically connected. Gate terminals 16 and 18 form the input terminal 24 of inverter 10, and drain terminals 20 and 22 form the output terminal 26 of inverter 10. The source terminal 28 of n-channel transistor 12 is electrically connected to a negative voltage supply conductor, -V.sub.dd, and the source terminal 30 of p-channel transistor 14 is electrically connected to a positive voltage supply conductor, +V.sub.dd, such that source terminals 28 and 30 form the bias voltage terminals of inverter 10. Inverter 10 provides at output terminal 26 an inverted CMOS logic signal relative to a CMOS logic signal applied to input terminal 24.
FIG. 2 shows a diagram of inverter 10 employed in the CMOS buffer circuit 32 of Magee. A pair of p- and n-channel offset transistors 34 and 36 provide offset voltages to n- and p-channel transistors 12 and 14, respectively. The offset voltages are developed and are applied to n- and p-channel transistors 12 and 14 as follows. The gate 38 and drain 40 terminals of p-channel offset transistor 34 are electrically connected to the negative voltage supply conductor, -V.sub.dd. The p-channel offset transistor 34 provides to its source terminal 42 and to the source terminal 28 of n-channel transistor 12 the voltage, -V.sub.dd, offset by an amount proportional to the p-channel threshold voltage. Similarly, the gate 44 and drain 46 terminals of n-channel offset transistor 36 are electrically connected to the positive voltage supply conductor, +V.sub.dd. The n-channel offset transistor 36 provides to its source terminal 48 and to the source terminal 30 of p-channel transistor 14 the voltage, +V.sub.dd, offset by an amount proportional to the n-channel threshold voltage. The input 24 and output 26 terminals of inverter 10 constitute the respective input and output terminals of buffer circuit 32.
The p- and n-channel offset transistors 34 and 36 together with the respective n- and p-channel transistors 12 and 14 of the inverter 10 form two symmetric pairs of complementary transistors, which cooperate to provide a logic threshold that is substantially independent of the different threshold voltage characteristics of the n- and p-channel transistors 12 and 14. This arrangement provides a stable logic threshold voltage that is midway between the voltages -V.sub.dd and +V.sub.dd. By comparison, inverter 10 without offset transistors 34 and 36 would have an imprecisely known logic threshold voltage that is generated by the varying threshold voltage characteristics of n-channel transistor 12 and p-channel transistor 14.
The CMOS buffer circuit 32 of Magee provides, however, suboptimal performance because of a high output impedance caused by negative current feedback during the switching of inverter 10. (Any output current flows through the impedance of one of the offset transistors 34 and 36, thereby decreasing the effective available drive voltage for transistors 12 and 14.) This reduces the ability of buffer circuit 32 to drive interconnect and load capacitance and limits the operation of the circuit to a maximum switching speed of about an order of magnitude slower than that of inverter 10 alone. The CMOS buffer circuit of Magee is, therefore, too slow to be employed in an interface between bipolar and CMOS digital circuits.